The invention relates to a Schmitt trigger circuit, and particularly to a Schmitt trigger circuit wherein the threshold voltage is set in two inverting amplifier circuits independently of each other to provide hysteresis characteristics.
Prior art techniques will be described in conjunction with FIGS. 6 and 7.
FIGS. 6 and 7 respectively illustrate a block diagram of a conventional Schmitt trigger circuit described in Japanese Patent Laid-Open No. 75024/1982 and a block diagram of a conventional Schmitt trigger circuit described in Japanese Utility Model Laid-Open No. 11550/1993. These Schmitt trigger circuit comprise two inverter circuits, different from each other in switching voltage (threshold voltage), and an R/S flip-flop circuit.
In FIG. 6, an R/S flip-flop circuit 618 comprises: an OR/NAND circuit 616 composed of a CMOS transistor; and an inverter circuit 615. CMOS inverters 611, 612 are provided in a set input system of flip-flop circuit 618, and CMOS inverters 613, 614 are provided in a reset input system of the flip-flop circuit 618. Thus, a Schmitt trigger circuit is constructed.
In this case, in order to obtain hysteresis characteristics, setting is performed in such a manner that, when the threshold voltages of inverters 611, 612, 613, and 614 are VT1, VT2, VT3, and VT4, respectively, a requirement of (VT1 =VT4) greater than (VT2=VT3) is satisfied.
On the other hand, in FIG. 7, two inverters of an inverter 713 and an inverter 714 different from each other in switching voltage (threshold voltage) are connected to respective inputs in a flip-flop comprising NAND gates 711 and 712 which have been connected so as to cross each other, and an input voltage Vin is applied to the input of each inverter. Thus, a Schmitt trigger circuit is constructed.
Here the inverter 713 comprises a p-channel transistor 716 and a high-resistance element 717 of polysilicon which have been connected in tandem between the power supply potential side and the ground potential side. The inverter 714 comprises a high-resistance element 718 of polysilicon and an n-channel transistor 719 which have been connected in tandem between the power supply potential side and the ground potential side.
Since the Schmitt trigger circuit shown in FIG. 6 comprises a CMOS transistor, no current flows when the input signal is in a stationary state, contributing to a reduction in power consumption. Due to a variation in conditions at the time of production and a variation in characteristics of each transistor, a variation in threshold voltage occurs in the inverters 611, 612, 613, 614. This greatly affects the hysteresis characteristics.
The Schmitt trigger circuit shown in FIG. 7 can improve hysteresis characteristics. In this Schmitt trigger circuit, however, a current flows also in the case where the input signal is in a stationary state. This leads to increased power consumption.
Accordingly, it is an object of the invention to provide a Schmitt trigger circuit which has improved hysteresis characteristics and is free from the flow of a stationary current.
According to the first feature of the invention, a Schmitt trigger circuit comprising:
a first inverting amplifier circuit comprising a first p-channel transistor, with a source connected to a power supply potential side, having a high set threshold voltage level and a first active load n-channel transistor with a source connected to a ground potential side, wherein the first p-channel transistor in its drain is connected to the first active load n-channel transistor in its drain and an input signal is supplied and connected to a gate in the first p-channel transistor while a first input signal level decision signal is output from the first p-channel transistor on its drain side;
a second inverting amplifier circuit comprising a second n-channel transistor, with a source connected to the ground potential side, having a low set threshold voltage level and a second active load p-channel transistor with a source connected to a power supply potential side, wherein the second n-channel transistor in its drain is connected to the second active load p-channel transistor in its drain and said input signal is supplied and connected to a gate in the second n-channel transistor while a second input signal level decision signal is output from the second n-channel transistor on its drain side; and
a flip-flop circuit into which the first input signal level decision signal is input as one input while the second input signal level decision signal is input as another input,
an output from the flip-flop circuit being used as an output signal, an inverted signal of the second input signal level decision signal being supplied and connected to the first active load n-channel transistor at its gate, an inverted signal of the first input signal level decision signal being supplied and connected to the second active load p-channel transistor at its gate.
Preferably, the Schmitt trigger circuit further comprises as a low-resistance load transistor for regulating the threshold voltage: a third p-channel transistor which is inserted into between the first p-channel transistor and the power supply potential side and has a gate connected to the ground potential; and a third n-channel transistor which is inserted into between the second n-channel transistor and the ground potential side and has a gate connected to the power supply potential.
Further, preferably, the Schmitt trigger circuit further comprises as a high-resistance load transistor for restricting a current: a fourth n-channel transistor which is inserted into between the first active load n-channel transistor and the ground potential side and has a gate connected to the power supply potential; and a fourth p-channel transistor which is inserted into between the second active load p-channel transistor and the power supply potential side and has a gate connected to the ground potential.
The Schmitt trigger circuit may comprise all of the third p-channel transistor and n-channel transistor and the fourth p-channel transistor and n-channel transistor.
The flip-flop circuit preferably comprises two two-input NAND circuits and one inversion circuit.
Alternatively, the flip-flop circuit may comprise two two-input NOR circuits and one inversion circuit.
Preferably, the Schmitt trigger circuit has been produced by a CMOS process.